Digital-PLL

M31 Digital-PLL is a core-power only programmable phase-locked loop (PLL) for frequency synthesis. It supports multiple modes of operation for several application conditions, such as Phase-locked loop (PLL) /Fractional-N phase-locked loop (FNPLL) /Spread spectrum clocking (SSC)/ Oscillator (OSC). M31 Digital-PLL has excellent immunity to power supply noise, making it ideally suited for use in noisy ASIC/SoC environments and is available as a single macro for easy integration into any ASIC/SoC.

Typical Phase Noise=-81.7dBc@1MHz
Period Jitter=1.3ps (std)
Block Diagram
  • IP Product Lists
  • Features
  • 4.8GHz low jitter fractional-N, Digital PLL, TSMC N6, 0.75V, N/S orientation
  • 4.8GHz low jitter fractional-N, Digital PLL, TSMC N7, 0.75V, N/S orientation
  • 4.8GHz low jitter fractional-N, Digital PLL, TSMC 12E, N/S orientation
  • 4.8GHz low jitter fractional-N, Digital PLL, TSMC 16FFC, N/S orientation
  • 3GHz, low jitter fractional-N, Digital PLL, TSMC 12FFC, N/S orientation
  • 3GHz, low jitter fractional-N, Digital PLL, TSMC 16FFC, N/S orientation
  • 1GHz, fractional-N Digital PLL, TSMC N12FFC, N/S orientation
  • 1GHz fractional-N, Digital PLL, TSMC 22ULL, N/S orientation
  • Pure core voltage design
  • Compact IP size (< 0.013mm²) and low power consumption (1.1mW @ 3GHz)
  • Compatible with commonly used crystal oscillator frequencies
  • Good power noise immunity for period jitter (< ±15%/V)
  • Supports 24-bit fractional accuracy
  • Supports down spread-spectrum clocking (SSC) technology
  • Supports retention OSC operation
  • Embedded lock-detect flag
  • Embedded scan chain for mass production
  • Full deliverables to ease ASIC/SoC integration
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