PCIe 3.1/2.1 PHY

M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 3.1 IP supports a complete range of PCIe 3.1 Base applications and is compliant with the PIPE 4.4.1 specification. The IP integrates high-speed mixed signal circuits to support 8Gbps PCIe 3.1 traffic and is backward compatible with 5.0Gbps PCIe 2.1 and 2.5Gbps PCIe 1.1 data rates. With the support of both TX and RX equalization techniques, the PCIe 3.1 IP is designed to meet the requirements of different channel conditions.

PCIe G3 Block Diagram
PCIe G3 Add-in Card Far-End Eye Test
PCIe G3 Add-in Card Rx Jitter Tolerance
PCIe G2 Add-in Card Far-End Eye Test
PCIe G2 Add-in Card Rx Jitter Tolerance
  • IP Product Lists
  • PCIe 3.1 Features
  • PCIe 2.1 Features
  • PCIe Gen3 PHY, x4-lane, RC/EP, SamSung 14LPP, N/S orientation
  • PCIe Gen3 PHY, x2-lane, RC/EP, SamSung 14LPP, N/S orientation
  • PCIe Gen3 PHY, x1-lane, RC/EP, SamSung 28FDSOI, N/S orientation
  • PCIe Gen3 PHY, x2-lane, RC/EP, TSMC N7, N/S orientation
  • PCIe Gen3 PHY, x1-lane, RC/EP, TSMC N7, N/S orientation
  • PCIe Gen3 PHY, x4-lane, RC/EP, TSMC 12FFC, N/S orientation
  • PCIe Gen3 PHY, x1-lane, RC/EP, TSMC 12FFC, N/S orientation
  • PCIe Gen3 PHY, x4-lane, RC/EP, TSMC 16FFC, N/S orientation
  • PCIe Gen3 PHY, x1-lane, RC/EP, TSMC 16FFC, N/S orientation
  • PCIe Gen3 PHY, x4-lane, RC/EP, TSMC 22ULP 1.8V, N/S orientation
  • PCIe Gen3 PHY, x1-lane, RC/EP, TSMC 22ULL 1.8V, N/S orientation
  • PCIe Gen3 PHY, x1-lane, RC/EP, TSMC 22ULP 1.8V, N/S orientation
  • PCIe Gen3 PHY, x4-lane, RC/EP, TSMC 28HPC+, N/S orientation
  • PCIe Gen3 PHY, x2-lane, RC/EP, TSMC 28HPC+, N/S orientation
  • PCIe Gen3 PHY, x4-lane, RC/EP, UMC 28HPC+, N/S orientation
  • PCIe Gen3 PHY, x2-lane, RC/EP, UMC 28HPC+, N/S orientation
  • PCIe Gen3 PHY, x4-lane, EP, SMIC 40LL
  • PCIe Gen3 PHY, x2-lane, EP, SMIC 40LL
  • PCIe Gen2 PHY, x1-lane, RC/EP, TSMC 22ULL 1.8V, N/S orientation
  • PCIe Gen2 PHY, x1-lane, RC/EP, TSMC 22ULP 1.8V, N/S orientation
  • PCIe Gen2 PHY, x4-lane, RC/EP, TSMC 28HPC+, N/S orientation
  • PCIe Gen2 PHY, x2-lane, RC/EP, TSMC 28HPC+, N/S orientation
  • PCIe Gen2 PHY, x1-lane, RC/EP, TSMC 28HPC+, N/S orientation
  • PCIe Gen2 PHY, x1-lane, EP, TSMC 40LP
  • PCIe Gen2 PHY, x4-lane, EP, UMC 28HPC+, N/S orientation
  • PCIe Gen2 PHY, x4-lane, EP, SMIC 40LL
  • PCIe Gen2 PHY, x2-lane, EP, SMIC 40LL
More
  • Fully compliant with PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
  • Compliant with PIPE4.4.1 (PCIe) specification
  • Supports all power saving modes (P0, P0s, P1, P2) defined in the PIPE4.4.1 specification
  • Supports L1 PM Substates with CLKREQ#
  • Supports L1 Clock Power Management (CPM) with CLKREQ#
  • Supports Separate Refclk Independent SSC (SRIS) architecture
  • Accessible register controls allow user-specific optimization of critical parameters (e.g., TXPLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength)
  • Supports robust BIST functions for mass production testing
  • (Option) Dual-mode reference clock pad: Output 100MHz clock reference clock for RC mode or receive 100MHz clock for EP mode
  • Can be configured up to multi-lane (x2, x4) design with multiple instances
  • Fully compliant with PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
  • Compliant with PIPE4.4.1 (PCIe) specification
  • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
  • Supports L1 PM Substates with CLKREQ#
  • Supports L1 Clock Power Management (CPM) with CLKREQ#
  • Supports Separate Refclk Independent SSC (SRIS) architecture
  • Accessible register controls allow user-specific optimization of critical parameters (e.g., TXPLL bandwidth, TX de-emphasis level, CDR bandwidth, and EQ strength)
  • Supports robust BIST functions for mass production testing
  • Dual-mode reference clock pad: Output 100MHz clock reference clock for RC mode or receive 100MHz clock for EP mode
  • Can be configured up to multi-lane (x2, x4) design with multiple instances
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