Standard Cell Library

M31 provides a variety of cell libraries, including Ultra-High Density Standard Cell Library (HDSC), General Purpose Standard Cell library (GPSC), Ultra-High Speed Standard Cell library (HSSC), and Low Leakage Standard Cell library (LLSC). In addition to these base libraries, M31 also provides Engineering Change Order library (ECO) for metal programmable features, as well as Power Management Kit library (PMK) and Low Power Optimization Kit (LPKT) for power and speed optimization purposes. Nowadays, M31 Standard Cell Libraries are already applied in many fields such as IoT, AI, Automotive, and CPU/GPU markets.

M31 is able to customize specific cell functions and willing to cooperate with customers to achieve their PPA targets. Not only are Standard Cell Library solutions available for a wide range of process nodes between 12nm–180nm, but those IPs have also been silicon-proven.

Standard Cell Library IP Portfolio

Products
Features 
 IP Track
Standard Cell Library

High Density Standard Cell (HDSC)

5T, 6T, 6.5T, 7T 

General Purpose Standard Cell (GPSC)

9T

High Speed Standard Cell (HSSC)

12T

Low Leakage Standard Cell (LLSC)

5T, 7T, 8T, 9T, 10T

Sub-set:
 -Power Management Kit (PMK)

 -Low Power Optimization Kit (LPKT)

 -High Performance Kit (HPKT)
 -Engineering Change Order (ECO)

6T~12TM31 Foundation IPs at TSMC 90BCD Process

Standard Cell Library(Base)

Library

Features

Detail
Base

Basic cell for logic operation

  • High density track cell 

    General purpose track

  • High speed cell track

Standard Cell Library(Sub-set)

Library

Features

Detail

PMK

(power management kit)

  • Power management with switch cells and retention FF 

  • Level-shifter and isolation cells

  • High density track cell 

  • General purpose track

LPKT

(low power optimization kit)

  • Dynamic power optimization with CLK gating cells

  • Multi-bit FF

  • Fine grain cells

  • High density track cell 

  • General purpose track

HPKT

(high performance kit)

  • High performance optimization cells

  • Skew (optimized P/N ratio) cells

  • Optimizing CK2Q/ setup-hold

  • General purpose track

  • High speed cell track

ECO

Metal change for basic function modification

  • High density track cell

  • General purpose track
  • IP Product Lists
  • Features
  • M31 Foundation IPs at TSMC 12E Process
  • M31 Foundation IPs at TSMC 28HPC+ Process
  • M31 Foundation IPs at TSMC 28ESF3 Process
  • M31 Foundation IPs at TSMC 28HV Process
  • M31 Foundation IPs at TSMC 40LP Process
  • M31 Foundation IPs at TSMC 40HV Process
  • M31 Foundation IPs at TSMC 55LP Process
  • M31 Foundation IPs at TSMC 55ULP Process
  • M31 Foundation IPs at TSMC 55ULPEF Process
  • M31 Foundation IPs at TSMC 55BCD Process
  • M31 Foundation IPs at TSMC 90BCD Process
  • M31 Foundation IPs at TSMC 110HV Process
  • M31 Foundation IPs at TSMC 152GPIIA Process
  • M31 Foundation IPs at TSMC 180BCDIII Process
  • M31 Foundation IPs at GF 28SLP-HV Process
  • M31 Foundation IPs at GF 40HV Process
  • M31 Foundation IPs at GF 110TS Process
  • M31 Foundation IPs at GF 130BCD Process
  • M31 Foundation IPs at GF 130BCDLite Process
  • M31 Foundation IPs at GF 130BCDLite2 Process
  • M31 Foundation IPs at GF 150MCU Process
  • M31 Foundation IPs at GF 180MCU Process
  • M31 Foundation IPs at GF 180BCDLite Process
  • M31 Foundation IPs at SKHynix 90CIS Process
  • M31 Foundation IPs at SKHynix 110LP Process
  • M31 Foundation IPs at SKHynix 180ECD_ENH Process
  • M31 Foundation IPs at SKHynix 180ECD_ENH3 Process
  • M31 Foundation IPs at SKHynix 180ECD_ELL Process
  • M31 Foundation IPs at PSMC 40L Process
  • M31 Foundation IPs at PSMC 40HV Process
  • M31 Foundation IPs at PSMC 90A Process
  • M31 Foundation IPs at PSMC 90HV Process
  • M31 Foundation IPs at PSMC 110HV Process
  • M31 Foundation IPs at Winbond 55eNVM Process
  • M31 Foundation IPs at Winbond 90eNVM Process
  • M31 Foundation IPs at VIS 180HV Process
  • M31 Foundation IPs at TowerJazz 65BCD Process
  • M31 Foundation IPs at NexChip 40HV Process
  • M31 Foundation IPs at NexChip 90MP Process
  • M31 Foundation IPs at NexChip 110N Process
  • M31 Foundation IPs at NexChip 150BCD Process
  • M31 Foundation IPs at NexChip 150S Process
  • M31 Foundation IPs at NexChip 150HS Process
  • M31 Foundation IPs at NexChip 150FPS Process
  • M31 Foundation IPs at HLMC 28HKC+ Process
  • M31 Foundation IPs at HLMC 28LP Process
  • M31 Foundation IPs at HLMC 40LP Process
  • M31 Foundation IPs at HLMC 55LP Process
  • M31 Foundation IPs at HLMC 55HR Process
  • M31 Foundation IPs at HHGrace 40LP Process
  • M31 Foundation IPs at HHGrace 55LP Process
  • M31 Foundation IPs at HHGrace 55EF Process
  • M31 Foundation IPs at HHGrace 110G Process
  • M31 Foundation IPs at HHGrace 115EF Process
  • M31 Foundation IPs at HHGrace 130EF Process
  • M31 Foundation IPs at HHGrace 180ULL Process
  • M31 Foundation IPs at SMIC 40LL Process
  • M31 Foundation IPs at SMIC 40ULP Process
More
  • Ultra-High-Density Standard Cell Library (HDSC) for highest density, lowest cost and lowest power
  • General Purpose Standard Cell Library (GPSC) for general purpose logic with balanced PPA
  • Ultra-High Speed Standard Cell Library (HSSC) for the optimized performance in the critical path
  • Low Leakage Standard Cell library (LLSC) for ultra-low-leakage
  • Optimized cell sets for synthesis use with multiple cell variants and drive strengths
  • Accurate characterization by industry’s proven EDA/SPICE tool, and corner specified extraction at advanced nodes is also considered
  • Multi-operating voltage solution (voltage island)
  • Retention power solution (power-gating)
  • Fusion mixed-Vt solution (multi-Vt)
  • Multiple channel length swappable feasibility (leakage control)
  • Metal programmable for Engineering change feature (ECO library)
  • DFM compliant (uni-direction, dummy)
  • Super high routability (fully customized layout)
  • Multi-bit flip-flop for low-power application
  • Always on block ultra-low-leakage solution (Thick-Gate library)
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